Researchers speed up EUV mask optimization for advanced chipmaking

By AI, Created 4:47 PM UTC, May 18, 2026, /AGP/ – A Huazhong University of Science and Technology team says it has built a full-chip EUV curvilinear mask optimization framework that blends deep learning with gradient-based inverse optimization. The approach is designed to cut the computing cost of advanced lithography while keeping accuracy high enough for practical use in next-generation chip manufacturing.

Why it matters: - Full-chip EUV mask optimization has been a computational bottleneck for advanced integrated circuit manufacturing. - The new framework is designed to make curvilinear mask design more practical for EUV lithography, where precision affects critical dimensions and chip performance. - The work could help support next-generation advanced nodes and future extensions such as high-NA EUV lithography and source-mask co-optimization.

What happened: - A team led by Prof. Shiyuan Liu at Huazhong University of Science and Technology reported a full-chip EUV curvilinear mask optimization framework in Light: Advanced Manufacturing. - The framework combines deep-learning-based forward modeling with gradient-based inverse optimization. - Doctoral student Pinxuan He is the first author. - Prof. Shiyuan Liu and Dr. Jiamin Liu are the co-corresponding authors. - Prof. Honggang Gu, Dr. Song Zhang, Prof. Qi Xia and Prof. Hao Jiang also contributed.

The details: - The team says the framework delivers an estimated speedup of four orders of magnitude over conventional FDTD methods while preserving accuracy. - A tunable U-Net surrogate model was trained on data generated from an EUV mask model based on the modified Born series. - The surrogate model represents three-dimensional thick mask effects through amplitude and phase perturbations. - Standardized preprocessing removes background noise and unwraps phase to reduce redundant interference from incident angles. - The result is faster prediction of mask near fields across multiple source points. - The study uses a slice-based gradient calculation scheme based on the adjoint method. - The scheme converts conventional full 3D field folding into a spatial unfolding approach. - The approach reduces gradient fluctuations along the depth direction. - The method requires only a single slice of the mask near field for gradient computation. - The method avoids storing the full 3D field data, which cuts memory use and supports large-scale parallel optimization. - The framework was tested on a BigMaC pattern with a wafer critical dimension of 19.41 nm. - Optimization ran in three stages with source points increasing over time. - The cost function converged steadily during the run. - The optimized mask patterns compensated for thick mask effects. - Wafer imaging contours improved and matched the target contours more closely. - Relative errors between the surrogate model and the reference model stayed below 3.5% in critical dimension measurements. - The DOI is 10.37188/lam.2026.049, and the source URL is the published paper.

Between the lines: - The technical goal here is not just better simulation, but simulation that is fast enough to fit real engineering workflows. - The combination of a learned surrogate model and a lower-memory gradient method suggests the team is trying to solve both speed and scalability at once. - The emphasis on curvilinear masks reflects a broader shift in lithography toward more flexible pattern shapes to widen process windows.

What’s next: - The team says the framework can be extended to high-NA EUV lithography and source-mask co-optimization. - The approach may give chipmakers a more practical path to full-chip EUV mask optimization in advanced manufacturing flows. - The work was supported by Chinese national, provincial and university funding programs.